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vpc 3205c, vpc 3215c video processor family edition oct. 19, 1998 6251-457-2pd prelimina r y d a t a sheet mic r onas micronas
vpc 3205c, vpc 3215c preliminary data sheet 2 micronas contents page section title 4 1. introduction 4 1.1. system architecture 4 1.2. video processor family 5 1.3. vpc applications 6 2. functional description 6 2.1. analog front-end 6 2.1.1. input selector 6 2.1.2. clamping 6 2.1.3. automatic gain control 6 2.1.4. analog-to-digital converters 6 2.1.5. digitally controlled clock oscillator 6 2.1.6. analog video output 7 2.2. adaptive comb filter 7 2.3. color decoder 8 2.3.1. if-compensation 8 2.3.2. demodulator 8 2.3.3. chrominance filter 9 2.3.4. frequency demodulator 9 2.3.5. burst detection 9 2.3.6. color killer operation 9 2.3.7. pal compensation/1-h comb filter 10 2.3.8. luminance notch filter 10 2.3.9. skew filtering 11 2.4. horizontal scaler 11 2.5. blackline detector 11 2.6. control and data output signals 11 2.6.1. line-locked clock generation 12 2.6.2. sync signals 12 2.6.3. digit3000 output format 12 2.6.4. line-locked 4:2:2 output format 12 2.6.5. line-locked 4:1:1 output format 12 2.6.6. output code levels 12 2.6.7. output signal levels 12 2.6.8. test pattern generator 13 2.6.9. priority bus codec 13 2.7. pal+ support 13 2.7.1. output signals for pal+/color+ support 15 2.8. video sync processing 17 3. serial interface 17 3.1. i 2 c-bus interface 17 3.2. control and status registers 29 3.2.1. calculation of vertical and east-west deflection coefficients 29 3.2.2. scaler adjustment
contents, continued page section title preliminary data sheet vpc 3205c, vpc 3215c micronas 3 31 4. specifications 31 4.1. outline dimensions 31 4.2. pin connections and short descriptions 33 4.3. pin descriptions (pin numbers for plcc68 package) 35 4.4. pin configuration 36 4.5. pin circuits 37 4.6. electrical characteristics 37 4.6.1. absolute maximum ratings 37 4.6.2. recommended operating conditions 38 4.6.3. recommended crystal characteristics 39 4.6.4. characteristics 39 4.6.4.1. characteristics, 5 mhz clock output 39 4.6.4.2. characteristics, 20 mhz clock input/output, external clock input (xtal1) 39 4.6.4.3. characteristics, reset input, test input 40 4.6.4.4. characteristics, priority, fpdat input/output 40 4.6.4.5. characteristics, vgav input 41 4.6.4.6. characteristics, i 2 c bus interface 41 4.6.4.7. characteristics, analog video inputs 41 4.6.4.8. characteristics, analog front-end and adcs 43 4.6.4.9. characteristics, output pin specification 44 4.6.4.10. characteristics, input pin specification 45 4.6.4.11. characteristics, clock output specification 46 5. application circuit 47 5.1. vga mode with vpc3215c 48 6. data sheet history
vpc 3205c, vpc 3215c preliminary data sheet 4 micronas video processor family release note: revision bars indicate significant changes to the previous edition. 1. introduction the vpc 32x5 is a high-quality, single-chip video front-end, which is targeted for 4:3 and 16:9, 50/60 and 100/120 hz tv sets. it can be combined with other members of the digit3000 ic family (such as cip 3250a, ddp 3300a, tpu 3040) and/or it can be used with 3rd-party products. the main features of the vpc 32x5 are ? all-digital video processing ? high-performance adaptive 4h comb filter y/c sepa- rator with adjustable vertical peaking ? multi-standard color decoder pal/ntsc/secam including all substandards ? 4 composite, 1 s-vhs input, 1 composite output ? integrated high-quality a/d converters and associ- ated clamp and agc circuits ? multi-standard sync processing ? linear horizontal scaling (0.25 ... 4), as well as non-linear horizontal scaling ?panorama vision? ? pal+ preprocessing (vpc 3215) ? line-locked clock, data and sync output (vpc 3215) ? display/deflection control (vpc 3205) ? submicron cmos technology ?i 2 c-bus interface ? one 20.25 mhz crystal, few external components ? 68-pin plcc package 1.1. system architecture fig. 1?1 shows the block diagram of the video proces- sor. 1.2. video processor family the vpc video processor family supports 15/32 khz systems and is available with different comb filter options. the 50 hz/single scan versions provide con- trolling for the display and the vertical/east west deflec- tion of ddp 3300a. the 100 hz/double scan versions have a line-locked clock output interface and the pal+ preprocessing option. table 1?1 gives an over- view of the vpc video processor family. fig. 1?1: vpc 32x5c block diagram table 1?1: vpc processor family features 50 hz/ single scan 100 hz/ double scan 4h comb filter vpc 32 05c vpc 32 15c 2h comb filter vpc 32 00a vpc 32 10a no comb filter vpc 32 01a vpc 32 11a v1 adaptive combfilter v2/y c v3 v4 cvbs out output formatter horizontal scaler panorama mode ntsc pal secam color decoder 2*adc, 8 bit front-end i 2 c i 2 c 20.25 mhz clock gen. dco sync processing line-locked clock synthesis yuv clock h/v
preliminary data sheet vpc 3205c, vpc 3215c micronas 5 1.3. vpc applications fig. 1 ? 2 depicts several vpc applications. since the vpc functions as a video front-end, it must be comple- mented with additional functionality to form a complete tv set. the ddp 33x0 contains the video back-end with video postprocessing (contrast, peaking, dti,...), h/v-deflec- tion, rgb insertion (scart, text, pip,...) and tube control (cutoff, white drive, beam current limiter). it generates a beam scan velocity modulation output from the digital yc r c b and rgb signals. note that this signal is not generated from the external analog rgb inputs. the cip 3250a provides a high quality analog rgb interface with character insertion capability. this allows appropriate processing of external sources, such as mpeg2 set-top boxes in transparent (4:2:2) quality. furthermore, it translates rgb/fastblank signals to the common digital video bus and makes those signals available for 100 hz upconversion or double scan pro- cessing. in some european countries (italy), this fea- ture is mandatory. the ip indicates memory based image processing, such as scan rate conversion, vertical processing (zoom), or pal+ reconstruction. examples: ? europe: 15 khz/50 hz 32 khz/100 hz interlaced ? us: 15 khz/60 hz 32 khz/60 hz non-interlaced note that the vpc supports memory based applica- tions through line-locked clocks, syncs, and data. cip may run either with the native digit3000 clock but also with a line-locked clock system. fig. 1 ? 2: vpc 32xx applications a) 15 khz application europe b) double scan application (us, japan) c) 100 hz application (europe) with rgb inputs a) b) c) rgb h/v rgb rgb defl. h/v h/v defl. defl. ddp 3310b ddp 3310b ddp 3300a ip ip vpc 321x cip 3250a vpc 321x cvbs rgb cvbs cvbs rgb vpc 320x
vpc 3205c, vpc 3215c preliminary data sheet 6 micronas 2. functional description 2.1. analog front-end this block provides the analog interfaces to all video inputs and mainly carries out analog-to digital conver- sion for the following digital video processing. a block diagram is given in fig. 2 ? 1. most of the functional blocks in the front-end are digi- tally controlled (clamping, agc, and clock-dco). the control loops are closed by the fast processor ( ? fp ? ) embedded in the decoder. 2.1.1. input selector up to five analog inputs can be connected. four inputs are for input of composite video or s-vhs luma signal. these inputs are clamped to the sync back porch and are amplified by a variable gain amplifier. one input is for connection of s-vhs carrier-chrominance signal. this input is internally biased and has a fixed gain amplifier. 2.1.2. clamping the composite video input signals are ac coupled to the ic. the clamping voltage is stored on the coupling capacitors and is generated by digitally controlled cur- rent sources. the clamping level is the back porch of the video signal. s-vhs chroma is also ac coupled. the input pin is internally biased to the center of the adc input range. 2.1.3. automatic gain control a digitally working automatic gain control adjusts the magnitude of the selected baseband by +6/ ? 4.5 db in 64 logarithmic steps to the optimal range of the adc. the gain of the video input stage including the adc is 213 steps/v with the agc set to 0 db. 2.1.4. analog-to-digital converters two adcs are provided to digitize the input signals. each converter runs with 20.25 mhz and has 8 bit res- olution. an integrated bandgap circuit generates the required reference voltages for the converters. the two adcs are of a 2-stage subranging type. 2.1.5. digitally controlled clock oscillator the clock generation is also a part of the analog front end. the crystal oscillator is controlled digitally by the control processor; the clock frequency can be adjusted within 150 ppm. 2.1.6. analog video output the input signal of the luma adc is available at the analog video output pin. the signal at this pin must be buffered by a source follower. the output voltage is 2 v, thus the signal can be used to drive a 75 ? line. the magnitude is adjusted with an agc in 8 steps together with the main agc. fig. 2 ? 1: analog front-end vin3 vin2 vin1 cin vin4 bias adc adc gain clamp input frequency reference generation dvco 150 ppm agc +6/ ? 4.5 db digital cvbs or luma digital chroma system clocks 20.25 mhz analog video output cvbs/y cvbs/y cvbs/y cvbs/y chroma mux
preliminary data sheet vpc 3205c, vpc 3215c micronas 7 2.2. adaptive comb filter the 4h adaptive comb filter is used for high-quality luminance/chrominance separation for pal or ntsc composite video signals. the comb filter improves the luminance resolution (bandwidth) and reduces interfer- ences like cross-luminance and cross-color. the adap- tive algorithm eliminates most of the mentioned errors without introducing new artifacts or noise. a block diagram of the comb filter is shown in fig. 2 ? 2. the filter uses four line delays to process the informa- tion of three video lines. to have a fixed phase rela- tionship of the color subcarrier in the three channels, the system clock (20.25 mhz) is fractionally locked to the color subcarrier. this allows the processing of all color standards and substandards using a single crys- tal frequency. the cvbs signal in the three channels is filtered at the subcarrier frequency by a set of bandpass/notch fil- ters. the output of the three channels is used by the adaption logic to select the weighting that is used to reconstruct the luminance/chrominance signal from the 4 bandpass/notch filter signals. by using soft mix- ing of the 4 signals switching artifacts of the adaption algorithm are completely suppressed. the comb filter uses the middle line as reference, therefore, the comb filter delay is two lines. if the comb filter is switched off, the delay lines are used to pass the luma/chroma signals from the a/d converters to the luma/chroma outputs. thus, the processing delay is always two lines. in order to obtain the best-suited picture quality , the user has the possibility to influence the behaviour of the adaption algorithm going from moderate combing to strong combing. therfore, the following three para- meters may be adjusted: ? hdg ( horizontal difference gain ) ? vdg ( vertical difference gain ) ? ddr ( diagonal dot reducer ) hdg typically defines the comb strength on horizontal edges. it determines the amount of the remaining cross-luminance and the sharpness on edges respec- tively. as hdg increases, the comb strength, e. g. cross luminance reduction and sharpness, increases. vdg typically determines the comb filter behaviour on vertical edges. as vdg increases, the comb strength, e. g. the amount of hanging dots, decreases. after selecting the combfilter performance in horizontal and vertical direction, the diagonal picture perfor- mance may further be optimized by adjusting ddr. as ddr increases, the dot crawl on diagonal colored edges is reduced. to enhance the vertical resolution of the the picture, the vpc 32x5 provides a vertical peaking circuitry. the filter gain is adjustable between 0 ? +6 db and a coring filter suppresses small amplitudes to reduce noise arti- facts. in relation to the comb filter, this vertical peaking widely contributes to an optimal two-dimensional reso- lution homogeneity. 2.3. color decoder in this block, the standard luma/chroma separation and multi-standard color demodulation is carried out. the color demodulation uses an asynchronous clock, thus allowing a unified architecture for all color stan- dards. a block diagram of the color decoder is shown in fig. 2 ? 4. the luma as well as the chroma processing, is shown here. the color decoder also provides several special modes, e.g. wide band chroma format which is intended for s-vhs wide bandwidth chroma. also, fil- ter settings are available for processing a pal+ helper signal. if the adaptive comb filter is used for luma chroma separation, the color decoder uses the s-vhs mode processing. the output of the color decoder is yc r c b in a 4:2:2 format. fig. 2 ? 2: block diagram of the adaptive comb filter (pal mode) 2h delay line 2h delay line cvbs input chroma input bandpass bandpass/ luma / chroma mixers luma output chroma output filter notch filter bandpass filter adaption logic
vpc 3205c, vpc 3215c preliminary data sheet 8 micronas 2.3.1. if-compensation with off-air or mistuned reception, any attenuation at higher frequencies or asymmetry around the color sub- carrier is compensated. four different settings of the if-compensation are possible (see fig. 2 ? 3): ? flat (no compensation) ? 6 db/octave ? 12 db/octave ? 10 db/mhz the last setting gives a very large boost to high fre- quencies. it is provided for secam signals that are decoded using a saw filter specified originally for the pal standard. fig. 2 ? 3: frequency response of chroma if-com- pensation 2.3.2. demodulator the entire signal (which might still contain luma) is quadrature-mixed to the baseband. the mixing fre- quency is equal to the subcarrier for pal and ntsc, thus achieving the chroma demodulation. for secam, the mixing frequency is 4.286 mhz giving the quadra- ture baseband components of the fm modulated chroma. after the mixer, a lowpass filter selects the chroma components; a downsampling stage converts the color difference signals to a multiplexed half rate data stream. the subcarrier frequency in the demodulator is gener- ated by direct digital synthesis; therefore, substan- dards such as pal 3.58 or ntsc 4.43 can also be demodulated. 2.3.3. chrominance filter the demodulation is followed by a lowpass filter for the color difference signals for pal/ntsc. secam re- quires a modified lowpass function with bell-filter char- acteristic. at the output of the lowpass filter, all luma information is eliminated. the lowpass filters are calculated in time multiplex for the two color signals. three bandwidth settings (nar- row, normal, broad) are available for each standard (see fig. 2 ? 5). for pal/ntsc, a wide band chroma fil- ter can be selected. this filter is intended for high bandwidth chroma signals, e.g. a nonstandard wide bandwidth s-vhs signal. fig. 2 ? 4: color decoder colorpll/coloracc 1 h delay mux mux crossswitch notch filter luma / cvbs luma chroma mixer lowpass filter phase/freq demodulator acc chroma if compensation dc-reject
preliminary data sheet vpc 3205c, vpc 3215c micronas 9 fig. 2 ? 5: frequency response of chroma filters 2.3.4. frequency demodulator the frequency demodulator for demodulating the se- cam signal is implemented as a cordic-structure. it calculates the phase and magnitude of the quadrature components by coordinate rotation. the phase output of the cordic processor is differ- entiated to obtain the demodulated frequency. after the deemphasis filter, the dr and db signals are scaled to standard c r c b amplitudes and fed to the cross- over-switch. 2.3.5. burst detection in the pal/ntsc-system the burst is the reference for the color signal. the phase and magnitude outputs of the cordic are gated with the color key and used for controlling the phase-lock-loop (apc) of the demodula- tor and the automatic color control (acc) in pal/ntsc. the acc has a control range of +30 ... ? 6 db. for secam decoding, the frequency of the burst is measured. thus, the current chroma carrier frequency can be identified and is used to control the secam processing. the burst measurements also control the color killer operation; they can be used for automatic standard detection as well. 2.3.6. color killer operation the color killer uses the burst-phase/burst-frequency measurement to identify a pal/ntsc or secam color signal. for pal/ntsc, the color is switched off (killed) as long as the color subcarrier pll is not locked. for secam, the killer is controlled by the toggle of the burst frequency. the burst amplitude measurement is used to switch-off the color if the burst amplitude is below a programmable threshold. thus, color will be killed for very noisy signals. the color amplitude killer has a programmable hysteresis. 2.3.7. pal compensation/1-h comb filter the color decoder uses one fully integrated delay line. only active video is stored. the delay line application depends on the color stan- dard: ? ntsc: 1-h comb filter or color compensation ? pal: color compensation ? secam: crossover-switch in the ntsc compensated mode, fig. 2 ? 6 c), the color signal is averaged for two adjacent lines. thus, cross-color distortion and chroma noise is reduced. in the ntsc 1-h comb filter mode, fig. 2 ? 6 d), the delay line is in the composite signal path, thus allowing reduction of cross-color components, as well as cross-luminance. the loss of vertical resolution in the luminance channel is compensated by adding the ver- tical detail signal with removed color information. if the 4h adaptive comb filter is used, the 1-h ntsc comb filter has to be deselected. pal/ntsc secam
vpc 3205c, vpc 3215c preliminary data sheet 10 micronas fig. 2 ? 6: ntsc color decoding options fig. 2 ? 7: pal color decoding options fig. 2 ? 8: secam color decoding 2.3.8. luminance notch filter if a composite video signal is applied, the color infor- mation is suppressed by a programmable notch filter. the position of the filter center frequency depends on the subcarrier frequency for pal/ntsc. for secam, the notch is directly controlled by the chroma carrier frequency. this considerably reduces the cross-lumi- nance. the frequency responses for all three systems are shown in fig. 2 ? 9. fig. 2 ? 9: frequency responses of the luma notch filter for pal, ntsc, secam 2.3.9. skew filtering the system clock is free-running and not locked to the tv line frequency. therefore, the adc sampling pat- tern is not orthogonal. the decoded yc r c b signals are converted to an orthogonal sampling raster by the skew filters, which are part of the scaler block. the skew filters are controlled by a skew parameter and allow the application of a group delay to the input signals without introducing waveform or frequency response distortion. the amount of phase shift of this filter is controlled by the horizontal pll1. the accuracy of the filters is 1/32 clocks for luminance and 1/4 clocks for chroma. thus the 4:2:2 yc r c b data is in an orthogonal pixel format even in the case of nonstandard input signals such as vcr. chroma notch filter 8 chroma process. cvbs y 1 h delay 8 cvbs chroma process. notch filter y 8 chroma process. luma y 8 c c r b c c r b c c r b notch filter 1 h delay 8 chroma process. cvbs y c c r b d) comb filter c) compensated a) conventional b) s-vhs chroma notch filter 1 h delay 8 chroma process. cvbs y 8 chroma process. luma y 8 1 h delay c c r b c c r b a) conventional b) s-vhs mux notch filter 1 h delay 8 chroma process. cvbs y c c r b db mhz 10 02 4 68 10 0 ? 10 ? 20 ? 30 ? 40 db mhz 10 02 4 68 10 0 ? 10 ? 20 ? 30 ? 40 pal/ntsc notch filter secam notch filter
preliminary data sheet vpc 3205c, vpc 3215c micronas 11 2.4. horizontal scaler the 4:2:2 ycrcb signal from the color decoder is pro- cessed by the horizontal scaler. the scaler block allows a linear or nonlinear horizontal scaling of the input video signal in the range of 0.25 to 4. nonlinear scaling, also called ? panorama vision ? , provides a geometrical distortion of the input picture. it is used to fit a picture with 4:3 format on a 16:9 screen by stretch- ing the picture geometry at the borders. also, the inverse effect can be produced by the scaler. a sum- mary of scaler modes is given in table 2 ? 1. the scaler contains a programmable decimation filter, a 1-line fifo memory, and a programmable interpola- tion filter. the scaler input filter is also used for pixel skew correction, see 2.3.9. the decimator/interpolator structure allows optimal use of the fifo memory. the controlling of the scaler is done by the internal fast processor. 2.5. blackline detector in case of a letterbox format input video, e.g. cinema- scope, pal+ etc., black areas at the upper and lower part of the picture are visible. it is suitable to remove or reduce these areas by a vertical zoom and/or shift operation. the vpc 32xx supports this feature by a letterbox detector. the circuitry detects black video lines by measuring the signal amplitude during active video. for every field the number of black lines at the upper and lower part of the picture are measured, compared to the previous measurement and the minima are stored in the i 2 c-register blklin. to adjust the picture amplitude, the external controller reads this register, calculates the vertical scaling coefficient and transfers the new settings, e.g. vertical sawtooth parameters, horizontal scaling coefficient etc., to the vpc. letterbox signals containing logos on the left or right side of the black areas are processed as black lines, while subtitles, inserted in the black areas, are pro- cessed as non-black lines. therefore the subtitles are visible on the screen. to suppress the subtitles, the vertical zoom coefficient is calculated by selecting the larger number of black lines only. dark video scenes with a low contrast level compared to the letterbox area are indicated by the blkpic bit. 2.6. control and data output signals the vpc 32xx supports two output modes: in digit3000 mode, the output interfaces run at the main system clock, in line-locked mode, the vpc generates an asynchronous line-locked clock that is used for the output interfaces. 2.6.1. line-locked clock generation an on-chip rate multiplier will be used to synthesize any desired output clock frequency of 13.5/16/18 mhz. a double clock frequency output is available to support 100 hz systems. the synthesizer is controlled by the embedded risc controller, which also controls all front-end loops (clamp, agc, pll1, etc.). this allows the generation of a line-locked output clock regardless of the system clock (20.25 mhz) which is used for comb filter operation and color decoding. the control of scaling and output clock frequency is kept indepen- dent to allow aspect ratio conversion combined with sample rate conversion. the line-locked clock circuity generates control signals, e.g. horizontal/vertical sync, active video output, it is also the interface from the internal (20.25 mhz) clock to the external line-locked clock system. if no line-locked clock is required, i.e. in the digit3000 mode, the system runs at the 20.25 mhz main clock. the horizontal timing reference in this mode is pro- vided by the front-sync signal. in this case, the line-locked clock block and all interfaces run from the 20.25 mhz main clock. the synchronization signals from the line-locked clock block are still available, but for every line the internal counters are reset with the main-sync signal. a double clock signal is not available in digit3000 mode. table 2 ? 1: scaler modes mode scale factor description compression 4:3 16:9 0.75 linear 4:3 source displayed on a 16:9 tube, with side panels panorama 4:3 16:9 non- linear compr 4:3 source displayed on a 16:9 tube, borders distorted zoom 4:3 4:3 1.33 linear letterbox source (pal+) displayed on a 4:3 tube, vertical overscan with cropping of side panels panorama 4:3 4:3 non- linear zoom letterbox source (pal+) displayed on a 4:3 tube, vertical overscan, bor- ders distorted, no crop- ping 20.25 13.5 mhz 0.66 sample rate conversion to line-locked clock
vpc 3205c, vpc 3215c preliminary data sheet 12 micronas 2.6.2. sync signals the front end will provide a number of sync/control sig- nals which are output with the output clock. the sync signals are generated in the line-locked clock block. ? href : horizontal sync ? avo: active video out (programmable) ? hc: horizontal clamp (programmable) ? vref : vertical sync ? intlc: interlace ? helper: pal+ helper lines all horizontal signals are not qualified with field infor- mation, i.e. the signals are present on all lines. the horizontal timing is shown in fig. 2 ? 10. details of the horizontal/vertical timing are given in fig. 2 ? 14. 2.6.3. digit3000 output format the picture bus format between all digit3000 ics is 4:2:2 ycrcb with 20.25 mhz samples/s. only active video is transferred, synchronized by the system main sync signal (msy) which indicates the start of valid data for each scan line and which initializes the color multiplex. the video data is orthogonally sampled ycrcb, the output format is given in table 2 ? 2. the number of active samples per line is 1080 for all stan- dards (525 and 625). the output can be switched to 4:1:1 mode with the out- put format according to table 2 ? 3. via the msy line, serial data is transferred which con- tains information about the main picture such as cur- rent line number, odd/even field etc.). it is generated by the deflection circuitry and represents the orthogo- nal timebase for the entire system. 2.6.4. line-locked 4:2:2 output format in line-locked mode, the vpc 32xx will produce the industry standard pixel stream for yc r c b data. the dif- ference to digit3000 native mode is only the number of active samples, which of course, depends on the chosen scaling factor. thus, table 2 ? 2 is valid for both 4:2:2 modes. 2.6.5. line-locked 4:1:1 output format the orthogonal 4:1:1 output format is compatible to the industry standard. the yc r c b samples are skew-cor- rected and interpolated to an orthogonal sampling ras- ter (see table 2 ? 3). note: c* x y (x = pixel number and y = bit number) 2.6.6. output code levels output code levels correspond to itu-r code levels: y = 16...240 black level = 16 c r c b = 128 112 an overview over the output code levels is given in ta b l e 2 ? 4. 2.6.7. output signal levels all data and sync lines operate at ttl compliant lev- els. with an optional external 3.3 v supply for the out- put pins, reduced voltage swings can be obtained. 2.6.8. test pattern generator the yc r c b outputs can be switched to a test mode where yc r c b data are generated digitally in the vpc32xx. test patterns include luma/chroma ramps, flat field, and a pseudo color bar. table 2 ? 2: orthogonal 4:2:2 output format luma y 1 y 2 y 3 y 4 chroma c b1 c r1 c b3 c r3 table 2 ? 3: 4:1:1 orthogonal output format luma chroma y 1 y 2 y 3 y 4 c 3 , c 7 c 2 , c 6 c 1 , c 5 c 0 , c 4 c b1 7 c b1 6 c r1 7 c r1 6 c b1 5 c b1 4 c r1 5 c r1 4 c b1 3 c b1 2 c r1 3 c r1 2 c b1 1 c b1 0 c r1 1 c r1 0
preliminary data sheet vpc 3205c, vpc 3215c micronas 13 2.6.9. priority bus codec the vpc data outputs are controlled by the priority bus interface. this interface allows a maximum of 8 signal sources to be connected on a common video yc r c b bus. the 3-bit priority bus signal controls the arbitra- tion and source switching of the video sources on a pixel-by-pixel basis. the priority bus makes features possible, such as ? real time digital pip insertion ? teletext/mixed-mode picture insertion. in general, each source has its own yc r c b bus request. this bus request may either be software or hardware controlled, i.e. a fast blank signal. data colli- sion on the bus is avoided by a bus arbiter that pro- vides the individual bus grant in accordance to the user defined source priority. each master sends a bus request using his individual priority id onto the bus and immediately reads back the bus state. only in case of a positive arbitration, e.g. the master reads back his own priority id, the bus is granted to the master. 2.7. pal+ support for pal+, the vpc 321x provides basic helper prepro- cessing: ? a/d conversion (shared with the existing adcs) ? mixing with subcarrier frequency ? lowpass filter 2.5 mhz ? gain control by chroma acc ? delay compensation to composite video path ? helper window (line# identification) ? output at the luma output port helper signals are processed like the main video luma signals, i.e. they are subject to scaling, sample rate conversion and orthogonalization if activated. the adaptive comb filter processing is switched off for the helper lines. it is expected that further helper processing (e.g. non- linear expansion, matched filter) is performed outside the vpc. 2.7.1. output signals for pal+/color+ support for a pal+/color+ signal, the 625 line pal image con- tains a 16/9 core picture of 431 lines which is in stan- dard pal format. the upper and lower 72 lines contain the pal+ helper signal, and line 23 contains signalling information for the pal+ transmission. for pal+ mode, the y signal of the core picture, which is during lines 60 ? 274 and 372 ? 586, is replaced by the orthogonal composite video input signal. in order to fit the signal to the 8-bit port width, the adc signal ampli- tudes are used. during the helper window, which is in lines 24 ? 59, 275 ? 310, 336 ? 371, 587 ? 622, the demodu- lated helper is signal processed by the horizontal scaler and the output circuitry. it is available at the luma output port. the processing in the helper reference lines 23 and 623 is different for the wide screen signaling part and the black reference and helper burst signals. the code levels are given in detail in table 2 ? 4, the output signal for the helper reference line is shown in fig. 2 ? 11. table 2 ? 4: output signal code levels for pal/pal+ signal output signal luma outputs y[7:0] chroma outputs c[7:0] output format black/zero level amplitude output format amplitude standard ycrcb (100% chroma binary 16 224 offset binary 128 112 signed 112 cvbs, crcb binary 64 149 (luma) offset binary 128 112 signed 112 demodulated helper signed 0 109 ?? helper wss binary 68 149 (wss:106) ?? helper black level, ref. burst offset binary 128 19 (128 ? 109) ??
vpc 3205c, vpc 3215c preliminary data sheet 14 micronas fig. 2 ? 10: horizontal timing for line-locked mode fig. 2 ? 11: pal+ helper reference line output signal 131 16 line length (programmable) 0 line length/2 horizontal pixel counter horizontal sync (hs) horizontal clamp (hc) newline (internal signal) active video out (avo) vertical sync (vs), field 1 vertical sync (vs), field 2 field 1 field 2 start / stop programmable start of video output (programmable) start / stop programmable 174 68 255 helper burst (demodulated) wss signal 19 128 binary format 255 signed format 0 black level
preliminary data sheet vpc 3205c, vpc 3215c micronas 15 2.8. video sync processing fig. 2 ? 12 shows a block diagram of the front-end sync processing. to extract the sync information from the video signal, a linear phase lowpass filter eliminates all noise and video contents above 1 mhz. the sync is separated by a slicer; the sync phase is measured. a variable window can be selected to improve the noise immunity of the slicer. the phase comparator mea- sures the falling edge of sync, as well as the integrated sync pulse. the sync phase error is filtered by a phase-locked loop that is computed by the fp. all timing in the front-end is derived from a counter that is part of this pll, and it thus counts synchronously to the video signal. a separate hardware block measures the signal back porch and also allows gathering the maximum/mini- mum of the video signal. this information is processed by the fp and used for gain control and clamping. for vertical sync separation, the sliced video signal is integrated. the fp uses the integrator value to derive vertical sync and field information. the information extracted by the video sync process- ing is multiplexed onto the hardware front sync signal (fsy) and is distributed to the rest of the video pro- cessing system. the format of the front sync signal is given in fig. 2 ? 13. the data for the vertical deflection, the sawtooth, and the east-west correction signal is calculated by the vpc 32xx. the data is buffered in a fifo and trans- ferred to the back-end ic ddp 3300a by a single wire interface. frequency and phase characteristics of the analog video signal are derived from pll1. the results are fed to the scaler unit for data interpolation and orthogonal- ization and to the clock synthesizer for line-locked clock generation. horizontal and vertical syncs are latched with the line-locked clock. fig. 2 ? 12: sync separation block diagram fig. 2 ? 13: front sync format phase comparator & lowpass counter frontend timing front sync lowpass 1 mhz & syncslicer horizontal sync separation vertical sync separation fifo sawtooth video input skew front sync generator vertical serial data vertical sawtooth e/w parabola calculation clamping, colorkey, fifo_write pll1 clamp & signal meas. vblank field clock synthesizer syncs clock h/v syncs f1 input analog video fsy f1 f0 skew skew lsb not used fv msb (not in scale) f0 reserved 0 = field 1 1 = field 2 f: field # 0 = off 1 = on v: vertical sync parity
vpc 3205c, vpc 3215c preliminary data sheet 16 micronas fig. 2 ? 14: vertical timing of vpc 32x5 shown in reference to input video. video output signals are delayed by 3-h for comb filter version (vpc 32x5). 314 315 316 317 313 311 318 335 336 310 ccir 319 320 1234 623 5 6 23 24 ccir 78 field 1 field 2 >1 clk > 1clk vertical sync (vs) interlace (intlc) active video output (avo) helper ref line 23, 623 (internal signal) signal matches output video the following signals are identical for field1 / field2 helper lines 23 ? 59, 275 ? 310, 336 ? 371, 587 ? 623, signal matches output video 624 625 312 interlace (intlc) vertical sync (vs) front-sync (fsy)
preliminary data sheet vpc 3205c, vpc 3215c micronas 17 3. serial interface 3.1. i 2 c-bus interface communication between the vpc and the external controller is done via i 2 c-bus. the vpc has an i 2 c-bus slave interface and uses i 2 c clock synchroni- zation to slow down the interface if required. the i 2 c-bus interface uses one level of subaddress: one i 2 c-bus address is used to address the ic and a sub- address selects one of the internal registers. the i 2 c-bus chip address is given below: the registers of the vpc have 8 or 16-bit data size; 16-bit registers are accessed by reading/writing two 8-bit data words. figure 3 ? 1 shows i 2 c-bus protocols for read and write operations of the interface; the read operation requires an extra start condition and repetition of the chip address with read command set. 3.2. control and status registers ta bl e 3 ? 1 gives definitions of the vpc control and sta- tus registers. the number of bits indicated for each register in the table is the number of bits implemented in hardware, i.e. a 9-bit register must always be accessed using two data bytes but the 7 msb will be ? don ? t care ? on write operations and ? 0 ? on read opera- tions. write registers that can be read back are indi- cated in table 3 ? 1. functions implemented by software in the on-chip con- trol microprocessor (fp) are explained in table 3 ? 2. a hardware reset initializes all control registers to 0. the automatic chip initialization loads a selected set of registers with the default values given in table 3 ? 1. the register modes given in table 3 ? 1 are ? w: write only register ? w/r: write/read data register ? r: read data from vpc ? v: register is latched with vertical sync the mnemonics used in the intermetall vpc demo software are given in the last column. fig. 3 ? 1: i 2 c-bus protocols a6 a5 a4 a3 a2 a1 a0 r/w 10001111/0 p s 1 0 sda scl s s 1000 111 1000 111 wack ack w 0111 1100 0111 1100 ack ack s 1 or 2 byte data 1000 111 r high byte data low byte data p w r ack nak s p = = = = = = 0 1 0 1 start stop ack nak p i 2 c write access subaddress 7c i 2 c read access subaddress 7c ack
vpc 3205c, vpc 3215c preliminary data sheet 18 micronas table 3 ? 1: control and status registers i 2 c sub- address number of bits mode function default name fp interface h ? 35 8 r fp status bit [0] write request bit [1] read request bit [2] busy ? fpsta h ? 36 16 w bit[8:0] 9-bit fp read address bit[11:9] reserved, set to zero ? fprd h ? 37 16 w bit[8:0] 9-bit fp write address bit[11:9] reserved, set to zero ? fpwr h ? 38 16 w/r bit[11:0] fp data register, reading/writing to this register will autoincrement the fp read/ write address. only 16 bit of data are transferred per i 2 c telegram. ? fpdat black line detector h ? 12 16 w/r read only register, do not write to this register! after reading, lowlin and uplin are reset to 127 to start a new measure- ment. bit[6:0] number of lower black lines bit[7] always 0 bit[14:8] number of upper black lines bit[15] 0/1 normal/black picture ? blklin lowlin uplin blkpic pin circuits h ? 1f 16 w/r sync pins (hs, hc, avo, help, intlc, vs): bit[2:0] 0..7 output strength for sync pins (7 = tristate, 6 = weak ... 0 = strong) bit[3] 0/1 pushpull/tristate for avo pin bit[4] 0/1 pushpull/tristate for other sync pins bit[5] 0/1 synchronization/no synchronization with horizontal hs for signals vs and intlc clock pins (llc1, llc2): bit[6] 0/1 pushpull/tristate for llc1 bit[7] 0/1 pushpull/tristate for llc2 data pins (lb[7:0], cb[7:0]): bit[10:8] 0..7 output strength for data pins (7 = tristate, 6 = weak ... 0 = strong) bit[11] 0/1 tristate /pushpull for data pins bit[12] 0/1 half-cycle pull-up(digit3000)/pushpull for lb, cb (lcc) bit[13] reserved (set to 0) bit[14:15] output strength for llc1: ( ? 2, ? 1,0,1) 0 0 0 0 0 0 0 0 0 0 trpad sncstr avodis sncdis vasysel llc1dis llc2dis datstr daten lcpudis llc1str
preliminary data sheet vpc 3205c, vpc 3215c micronas 19 h ? 20 8 w/r sync generator control: bit[1:0] 00 avo and active y/c data at same time 01 avo precedes y/c data one clock cycle 10 avo precedes y/c data two clock cycles 11 avo precedes y/c data three clock cycles bit[2] 0/1 positive/negative polarity for hs signal bit[3] 0/1 positive/negative polarity for hc signal bit[4] 0/1 positive/negative polarity for avo signal bit[5] 0/1 positive/negative polarity for vs signal bit[6] 0/1 positive/negative polarity for help signal bit[7] 0/1 positive/negative polarity for intlc signal 0 0 0 0 0 0 0 syncmode avopre hsinv hcinv avoinv vsinv helpinv intlcinv h ? 30 8 w/r v-sync delay control: bit[7:0] vs delay (8 llc clock cycles per lsb) 0 vsdel vsdel priority bus h ? 23 8 w/r priority bus overwrite register bit [7:0] 8 bit mask, bit[x] = 1 : overwrite priority x 0 priovr h ? 24 8 w/r priority bus id register and control bit [2:0] 0..7 priority id, 0 highest bit [4:3] 0..3 pad driver strength, 0 (strong) to 3 (weak) bit [5] 0/1 output mode: digit3000/llc bit [6] 0/1 source for prio request: avo/active always bit [7] 0/1 disable/enable priority interface, if disabled data pins are tristate ! 0 0 0 0 0 priomode pid priostr omode pidsrc pide sync generator h ? 21 16 w/r line length: bit[10:0] line length register in llc mode, this register defines the cycle of the sync counter which generates the sync pulses. in llc mode, the synccounter counts from 0 to line length, so this register has to be set to ? number of pixels per line ? 1 ? . in digit3000 mode, line length has to be set to 1295 for correct adjustment of vertical signals. bit[15:11] reserved (set to 0) 1295 linlen h ? 26 16 w/r hc start: bit[10:0] hc start defines the beginning of the hc signal in respect to the value of the sync counter. bit[15:11] reserved (set to 0) 50 hcstrt h ? 27 16 w/r hc stop: bit[10:0] hc stop defines the end of the hc signal in respect to the value of the sync counter. bit[15:11] reserved (set to 0) 800 hcstop i 2 c sub- address number of bits mode function default name
vpc 3205c, vpc 3215c preliminary data sheet 20 micronas h ? 28 16 w/r avo start: bit[10:0] avo start defines the beginning of the avo signal in respect to the value of the sync counter. bit[11] reserved (set to 0) bit[12] 0/1 vertical window disable/enable bit[13] 0/1 vertical window 312/262 lines bit[15:14] ? 2..1 vertical window interlace offset 60 avstrt verwin h ? 29 16 w/r avo stop: bit[10:0] avo stop defines the end of the avo signal in respect to the value of the sync counter. bit[15:11] reserved for test picture generation (set to 0 in normal operation) bit[11] 0/1 disable/enable test pattern generator bit[13:12] luma output mode: 00 y = ramp (240 ... 17) 01 y = 16 10 y = 90 11 y = 240 bit[14] 0/1 chroma output: 422/411 mode bit[15] 0/1 chroma output: pseudo color bar/zero if lmode = 0 0 0 0 0 0 avstop colbaren lmode m411 cmode h ? 22 16 w/r newline: bit[10:0] newline defines the readout start of the next line inrespect to the value of the sync counter. the value of this register must be greater than 31 for correct operation and should be identical to avostart (recom- mended). in case of 1h-bypass mode for scaler block, newline has no function. bit[12:11] reserved (set to 0) bit[13] vertical free run mode enabled, the vertical frequency is selected via verwin (h ? 28) bit[15:14] reserved (set to 0) 50 0 newlin flw i 2 c sub- address number of bits mode function default name
preliminary data sheet vpc 3205c, vpc 3215c micronas 21 table 3 ? 2: control registers of the fast processor ? default values are initialized at reset ? * indicates: register is initialized according to the current standard when sdt register is changed. fp sub- address function default name standard selection h ? 20 standard select: bit[2:0] standard 0 pal b,g,h,i (50 hz) 4.433618 1 ntsc m (60 hz) 3.579545 2 secam (50 hz) 4.286 3 ntsc44 (60 hz) 4.433618 4 pal m (60 hz) 3.575611 5 pal n (50 hz) 3.582056 6 pal 60 (60 hz) 4.433618 7 ntsc comb (60 hz) 3.579545 bit[3] 0/1 mod standard modifier pal modified to simple pal ntsc modified to compensated ntsc secam modified to monochrome 625 ntscc modified to monochrome 525 bit[4] 0/1 pal+ mode off/on bit[5] 0/1 4-h comb mode bit[6] 0/1 s-vhs mode: the s-vhs/comb bits allow the following modes: 00 composite input signal 01 comb filter active 10 s-vhs input signal 11 cvbs mode (composite input signal, no luma notch) option bits allow to suppress parts of the initialization; this can be used for color standard search: bit[7] no hpll setup bit[8] no vertical setup bit[9] no acc setup bit[10] 4-h comb filter setup only bit[11] status bit, normally write 0. after the fp has switched to a new standard, this bit is set to 1 to indicate operation complete. standard is automatically initialized when the insel register is written. 0 0 0 0 0 0 sdt pal ntsc secam ntsc44 palm paln pal60 ntscc sdtmod palplus comb svhs sdtopt
vpc 3205c, vpc 3215c preliminary data sheet 22 micronas h ? 21 input select: writing to this register will also initialize the standard bit[1:0] luma selector 00 vin3 01 vin2 10 vin1 11 vin4 bit[2] chroma selector 0/1 vin1/cin bit[4:3] if compensation 00 off 01 6 db/okt 10 12 db/okt 11 10 db/mhz only for secam bit[6:5] chroma bandwidth selector 00 narrow 01 normal 10 broad 11 wide bit[7] 0/1 adaptive/fixed secam notch filter bit[8] 0/1 enable luma lowpass filter bit[10:9] hpll speed 00 no change 01 terrestrial 10 vcr 11 mixed bit[11] status bit, write 0, this bit is set to 1 to indicate operation complete. 0 1 0 2 0 0 3 insel vis cis ifc cbw fntch lowp hpllmd h ? 22 picture start position: this register sets the start point of active video and can be used e.g. for panning. the setting is updated when ? sdt ? register is updated or when the scaler mode register ? scmode ? is writ- ten. 0sfif h ? 23 luma/chroma delay adjust. the setting is updated when ? sdt ? register is updated. bit[5:0] reserved, set to zero bit[11:6] luma delay in clocks, allowed range is +1 ... ? 7 0ldly h ? 29 helper delay register (pal+ mode only) bit[11:0] delay adjust for helper lines adjustable from ? 96...96, 1 step corresponds to 1/32 clock 0 hlp_dly h ? 2f vga mode select, pull-in range is limited to 2% bit[1:0] 0 31.5 khz 1 35.2 khz 2/3 37.9 khz is set to 0 by fp if vga = 0 bit[10] 0/1 disable/enable vga mode bit[11] status bit, write 0, this bit is set to 1 to indicate operation complete. 0 0 vga_c vgamode vga fp sub- address function default name
preliminary data sheet vpc 3205c, vpc 3215c micronas 23 comb filter h ? 28 comb filter control register bit[1:0] notch filter select 00 flat frequency characteristic 01 min. peaked 10 med. peaked 11 max. peaked bit[3:2] diagonal dot reduction 00 min. reduction ... 11 max. reduction bit[4:5] horizontal difference gain 00 min. gain ... 11 max. gain bit[7:6] vertical difference gain 00 max. gain ... 11 min. gain bit[11:8] vertical peaking gain 0 no vertical peaking... 15 max. vertical peaking h ? e7 3 1 2 3 0 comb_uc nosel ddr hdg vdg vpk h ? 55 comb filter test register bit[1:0] reserved, set ot 0 bit[2] 0/1 disable/enable vertical peaking dc rejection filter bit[3] 0/1 disable/enable vertical peaking coring bit[11:4] reserved, set to 0 0 0 cmb_tst dcr cor color processing h ? 34 acc multiplier value for pal+ helper signal b[10:0] eeemmmmmmmm m * 2 ? e 1280 acch h ? 36 acc pal+ helper gain adjust, gain is referenced to pal burst, allowed values from 256..1023 a value of zero allows manual adjust of helper amplitude via acch 787 hlpgain h ? 39 amplitude killer level (0:killer disabled) 25 kilvl h ? 3a amplitude killer hysteresis 5 kilhy h ? 16c automatic helper disable for nonstandard signals bit[11:0] 0 automatic function disabled bit[1:0] 01 enable bit[11:2] 1..50 number of fields to switch on helper signal 0hlpdis h ? dc ntsc tint angle, 512 = /4 0 tint horizontal pll h ? aa h ? ab h ? ac h-pll gain setting, these registers are used to set the h-pll speed, pll speed selection is done via the input selection register dvco h ? f8 crystal oscillator center frequency adjust, ? 2048 ... 2047 ? 720 dvco h ? f9 crystal oscillator center frequency adjustment value for line-lock mode, true adjust value is dvco ? adjust. for factory crystal alignment, using standard video signal: disable autolock mode, set dvco = 0, set lock mode, read crystal offset from adjust register and use negative value for initial center fre- quency adjustment via dvco. read only adjust fp sub- address function default name
vpc 3205c, vpc 3215c preliminary data sheet 24 micronas h ? f7 crystal oscillator line-locked mode, lock command/status write: 100 enable lock 0 disable lock read: 0 unlocked >2047 locked 0xlck h ? b5 crystal oscillator line-locked mode, autolock feature. if autolock is enabled, crystal oscillator locking is started automatically. bit[11:0] threshold, 0:autolock off 400 autolck fp status register h ? 12 general purpose control bits bit[2:0] reserved, do not change bit[3] vertical standard force bit[8:4] reserved, do not change bit[9] disable flywheel interlace bit[11:10] reserved, do not change to enable vertical free run mode set vfrc to 1 and dflw to 0 0 1 vfrc dflw h ? 13 standard recognition status bit[0] 1 vertical lock bit[1] 1 horizontally locked bit[2] 1 no signal detected bit[3] 1 color amplitude killer active bit[4] 1 disable amplitude killer bit[5] 1 color ident killer active bit[6] 1 disable ident killer bit[7] 1 interlace detected bit[8] 1 no vertical sync detection bit[9] 1 spurious vertical sync detection bit[12:10] reserved ? asr h ? 14 input noise level, available only for vpc 3215c read only noise h ? cb number of lines per field, p/s: 312, n: 262 read only nlpf h ? 15 vertical field counter, incremented per field read only vcnt h ? 74 measured sync amplitude value, nominal: 768 (pal), 732 (ntsc) read only sampl h ? 31 measured burst amplitude read only bampl h ? f0 firmware version number bit[7:0] internal revision number bit[11:8] firmware release read only ? h ? f1 hardware version number bit[5:0] internal hardware revision number bit[11:6] hardware id, vpc 32x5c = 01 read only ? fp sub- address function default name
preliminary data sheet vpc 3205c, vpc 3215c micronas 25 scaler control register h ? 40 scaler mode register bit[1:0] scaler mode 0 linear scaling mode 1 nonlinear scaling mode, ? panorama ? 2 nonlinear scaling mode, ? waterglass ? 3 reserved bit[2] reserved, set to 0 bit[3] color mode select 0/1 4:2:2 mode / 4:1:1 mode bit[4] scaler bypass bit[5] reserved, set to 0 bit[6] luma output format 0 itu-r luma output format (16 ? 240) 1 cvbs output format bit[7] chroma output format 0/1 itu-r (offset binary) / signed bit[10:8] reserved, set to 0 bit[11] 0 scaler update command, when the registers are updated the bit is set to 1 0scmode pano s411 bye yof cof h ? 41 luma offset register bit[6:0] luma offset 0..127 itu-r output format: 57 cvbs output format: 4 this register is updated when the scaler mode register is written 57 yoffs h ? 42 active video length for 1h-fifo bit[11:0] length in pixels d3000 mode (1296/h)1080 llc mode (864/h)720 this register is updated when the scaler mode register is written 1080 fflim h ? 43 scaler1 coefficient: this scaler compresses the signal. for compression by a factor c, the value c*1024 is required. bit[11:0] allowed values from 1024... 4095 this register is updated when the scaler mode register is written. 1024 scinc1 h ? 44 scaler2 coefficient: this scaler expands the signal. for expansion by a factor c, the value 1/c*1024 is required. bit[11:0] allowed values from 256..1024 this register is updated when the scaler mode register is written. 1024 scinc2 h ? 45 scaler1/2 nonlinear scaling coefficient this register is updated when the scaler mode register is written. 0scinc h ? 47 ? h ? 4b scaler1 window controls, see table 5 12-bit registers for control of the nonlinear scaling this register is updated when the scaler mode register is written. 0 scw1_0 ? 4 h ? 4c ? h ? 50 scaler2 window controls, see table 5 12-bit registers for control of the nonlinear scaling this register is updated when the scaler mode register is written. 0 scw2_0 ? 4 fp sub- address function default name
vpc 3205c, vpc 3215c preliminary data sheet 26 micronas llc control register h ? 60 horizontal offset bit[11:0] offset between fsy and hs 0 llc_offset h ? 65 vertical freeze start freeze llc pll for llc_start < line number < llc_stop bit[11:0] allowed values from ? 156...+156 ? 10 llc_start h ? 66 vertical freeze stop freeze llc pll for llc_start < line number < llc_stop bit[11:0] allowed values from ? 156...+156 4 llc_stop h ? 69 h ? 6a 20 bit llc clock center frequency 13.5 mhz 174763 = h?02aaab 16 mhz ? 135927 = h ? fded08 18 mhz 174763 = h ? 02aaab 42 = h ? 02a 2731 = h ? aa b llc_clockh llc_clockl h ? 61 pll frequency limiter, 8% 13.5 mhz 54 16 mhz 48 18 mhz 54 54 llc_dflimit h ? 6d llc clock generator control word bit[4:0] hardware register shadow llc_clkc = 5 13.5 mhz llc_clkc = 3 16 mhz llc_clkc = 3 18 mhz bit[10:5] reserved bit[11] 0/1 enable/disable llc pll 2053 llc_clkc fp sub- address function default name
preliminary data sheet vpc 3205c, vpc 3215c micronas 27 table 3 ? 3: control registers of the fast processor that are used for the control of ddp 3300a ? this function is only available in the 50 hz version (vpc 320x) ? default values are initialized at reset ? * indicates: register is initialized according to the current standard when sdt register is changed fp sub- address function default name fp display control register h ? 130 white drive red (0...1023) 700 wdr 1) h ? 131 white drive green (0...1023) 700 wdg 1) h ? 132 white drive blue (0...1023) 700 wdb 1) h ? 139 internal brightness, picture (0 ..511), the center value is 256, the range allows for both increase and reduction of brightness. 256 ibr h ? 13c internal brightness, measurement (0...511), the center value is 256, the brightness for measurement can be set to measure at higher cutoff current. the measurement brightness is independent of the drive val- ues. 256 ibrm h ? 13a analog brightness for external rgb (0...511), the center value is 256, the range allows for both increase and reduction of brightness. 256 abr h ? 13b analog contrast for external rgb (0...511) 350 act 1) the white drive values will become active only after writing the blue value wdb, latching of new values is indi- cated by setting the msb of wdb. fp display control register, bcl h ? 144 bcl threshold current, 0...2047 (max adc output ~1152) 1000 bclthr h ? 142 bcl time constant 0...15 13 ... 1700 msec 15 bcltm h ? 143 bcl loop gain. 0..15 0 bclg h ? 145 bcl minimum contrast 0 ...1023 307 bclmin h ? 105 test register for bcl/eht comp. function, register value: 0 normal operation 1 stop adc offset compensation x>1 use x in place of input from measurement adc 0bcltst fp display control register, deflection h ? 103 interlace offset, ? 2048 ...2047 this value is added to the sawtooth output during one field. 0intlc h ? 102 discharge sample count for deflection retrace, sawtooth dac output impedance is reduced for dscc lines after vertical retrace. 7dscc h ? 11f vertical discharge value, sawtooth output value during discharge operation, typically same as a0 init value for sawtooth. ? 1365 dscv h ? 10b eht (electronic high tension) compensation coefficient, 0...511 0 eht h ? 10a eht time constant. 0 ..15 3.2 ...410 msec 15 ehttm
vpc 3205c, vpc 3215c preliminary data sheet 28 micronas control registers, continued fp sub- address function default name fp display control register fp display control register, vertical sawtooth h ? 110 dc offset of sawtooth output this offset is independent of eht compensation. 0ofs h ? 11b accu0 init value ? 1365 a0 h ? 11c accu1 init value 900 a1 h ? 11d accu2 init value 0 a2 h ? 11e accu3 init value 0 a3 fp display control register, east-west parabola h ? 12b accu0 init value ? 1121 a0 h ? 12c accu1 init value 219 a1 h ? 12d accu2 init value 479 a2 h ? 12e accu3 init value ? 1416 a3 h ? 12f accu4 init value 1052 a4
preliminary data sheet vpc 3205c, vpc 3215c micronas 29 3.2.1. calculation of vertical and east-west deflection coefficients in table 3 ? 4 the formula for the calculation of the deflection initialization parameters from the polynomi- nal coefficients a,b,c,d,e is given for the vertical and east-west deflection. let the polynomial be the initialization values for the accumulators a0..a3 for vertical deflection and a0..a4 for east-west deflection are 12-bit values. the coefficients that should be used to calculate the initialization values for different field frequencies are given below, the values must be scaled by 128, i.e. the value for a0 of the 50 hz vertical deflection is 3.2.2. scaler adjustment in case of linear scaling, most of the scaler registers need not be set. only the scaler mode, active video length, and the fixed scaler increments (scinc1/scinc2) must be written. the adjustment of the scaler for nonlinear scaling modes should use the parameters given in table 3 ? 5. an example for ? panorama vision ? mode with 13.5 mhz line-locked clock is depicted in fig. 3 ? 2. the figure shows the scaling of the input signal and the variation of the scaling factor during the active video line. the scaling factor starts below 1, i.e. for the borders the video data is expanded by scaler 2. the scaling factor becomes one and compression scaling is done by scaler 1. when the picture center is reached, the scal- ing factor is held constant. at the second border the scaler increment is inverted and the scaling factor changes back symmetrically. the picture indicates the function of the scaler increments and the scaler win- dow parameters. the correct adjustment requires that pixel counts for the respective windows are always in number of output samples of scaler 1 or 2. table 3 ? 4: tables for the calculation of initialization values for vertical sawtooth and east-west parabola p = a + b(x ? 0.5) + c(x ? 0.5) 2 + d(x ? 0.5) 3 + e(x ? 0.5) 4 a0 = (a 128 ? b 1365.3 + c 682.7 ? d 682.7) 128 vertical deflection 50 hz abcd a0 128 ? 1365.3 +682.7 ? 682.7 a1 899.6 ? 904.3 +1363.4 a2 296.4 ? 898.4 a3 585.9 vertical deflection 60 hz abcd a0 128 ? 1365.3 +682.7 ? 682.7 a1 1083.5 ? 1090.2 +1645.5 a2 429.9 ? 1305.8 a3 1023.5 east-west deflection 50 hz ab c d e a0 128 ? 341.3 1365.3 ? 85.3 341.3 a1 111.9 ? 899.6 84.8 ? 454.5 a2 586.8 ? 111.1 898.3 a3 72.1 ? 1171.7 a4 756.5 east-west deflection 60 hz ab c d e a0 128 ? 341.3 1365.3 ? 85.3 341.3 a1 134.6 ? 1083.5 102.2 ? 548.4 a2 849.3 ? 161.2 1305.5 a3 125.6 ? 2046.6 a4 1584.8
vpc 3205c, vpc 3215c preliminary data sheet 30 micronas fig. 3 ? 2: scaler operation for ? panorama ? mode at 13.5 mhz border center border input signal video signal output signal compression ratio 1 expansion (scaler2) compression (scaler1) 234 01 scaler window cutpoints compression (scaler1) scinc2 scinc1 expansion (scaler2) scinc table 3 ? 5: set-up values for nonlinear scaler modes mode digit3000 (20.25 mhz) llc (13.5 mhz) register ? waterglass ? border 35% ? panorama ? border 30% ? waterglass ? border 35% ? panorama ? border 30% center 3/4 center 5/6 center 4/3 center 6/5 center 3/4 center 5/6 center 4/3 center 6/5 scinc1 1643 1427 1024 1024 2464 2125 1024 1024 scinc2 1024 1024 376 611 1024 1024 573 914 scinc 90 56 85 56 202 124 190 126 fflim 945 985 921 983 719 719 681 715 scw1 ? 0 110 115 83 94 104 111 29 13 scw1 ? 1 156 166 147 153 104 111 115 117 scw1 ? 2 317 327 314 339 256 249 226 241 scw1 ? 3 363 378 378 398 256 249 312 345 scw1 ? 4 473 493 461 492 360 360 341 358 scw2 ? 0 110 115 122 118 104 111 38 14 scw2 ? 1 156 166 186 177 104 111 124 118 scw2 ? 2 384 374 354 363 256 249 236 242 scw2 ? 3 430 425 418 422 256 249 322 346 scw2 ? 4 540 540 540 540 360 360 360 360
preliminary data sheet vpc 3205c, vpc 3215c micronas 31 4. specifications 4.1. outline dimensions fig. 4 ? 1: 68-pin plastic leaded chip carrier package (plcc68) weight approximately 4.8 g dimensions in mm 4.2. pin connections and short descriptions nc = not connected lv = if not used, leave vacant x = obligatory; connect as described in circuit diagram x 45 1.1 25.125 0.125 0.22 0.07 1.2 x 45 16 x 1.27 = 20.32 0.1 0.1 24.22 0.1 2 43 27 26 10 9 61 9 44 60 1 0.48 0.711 1.9 4.05 0.1 4.75 0.15 1.27 0.1 2 15 9 1.27 0.1 16 x 1.27 = 20.32 0.1 0.1 24.22 0.1 0.9 23.4 spgs7004-3/5e 25.125 0.125 1.6 pin no. plcc 68-pin pin name type connection (if not used ) short description 1gnd f supply x ground, analog front-end 2gnd f supply x ground, analog front-end 3 clk5 out lv ccu 5 mhz clock output 4v stby supply x standby supply voltage 5 xtal2 out x analog crystal output 6 xtal1 in x analog crystal input 7gnd f supply x ground, analog front-end 9gnd p supply x ground, output pad circuitry 10 intlc out lv interlace output 12 vs out lv vertical sync pulse 13 fsy out lv front sync pulse 14 msy/hs in/out lv main sync/horizontal sync pulse 15 helper out lv helper line output
vpc 3205c, vpc 3215c preliminary data sheet 32 micronas 16 hc in/out lv horizontal clamp pulse 17 avo out lv active video output 18 llc2 out lv double output clock 19 llc1 in/out lv output clock 20 y7 out gnd p picture bus luma (msb) 21 y6 out gnd p picture bus luma 22 y5 out gnd p picture bus luma 23 y4 out gnd p picture bus luma 24 y3 out gnd p picture bus luma 25 y2 out gnd p picture bus luma 26 gnd p x ground, output pad circuitry 28 y1 out gnd p picture bus luma 29 y0 out gnd p picture bus luma (lsb) 30 clk20 in/out lv main clock output 20.25 mhz 31 v supd supply x supply voltage, digital circuitry 34 gnd d supply x ground, digital circuitry 35 gnd p supply x ground, output pad circuitry 36 v supp supply x supply voltage, output pad supply 38 c7 out gnd p picture bus chroma (msb) 39 c6 out gnd p picture bus chroma 40 c5 out gnd p picture bus chroma 41 c4 out gnd p picture bus chroma 42 c3 out gnd p picture bus chroma 43 c2 out gnd p picture bus chroma 46 c1 out gnd p picture bus chroma 47 c0 out gnd p picture bus chroma (lsb) 48 pr0 in/out lv picture bus priority (lsb) 49 pr1 in/out lv picture bus priority 50 pr2 in/out lv picture bus priority (msb) 51 gnd p supply x ground, output pad circuitry 52 vgav in gnd p vgav input pin no. plcc 68-pin pin name type connection (if not used ) short description
preliminary data sheet vpc 3205c, vpc 3215c micronas 33 *) chroma selector must be set to 1 (cin chroma select) 4.3. pin descriptions (pin numbers for plcc68 package) pin 1 ? ground, analog front-end gnd f pin 2 ? ground, analog front-end gnd f pin 3 ? ccu 5 mhz clock output clk5 (fig. 4 ? 11) this pin provides a clock frequency for the tv micro- controller, e.g. a ccu 3000 controller. it is also used by the ddp 3300a display controller as a standby clock. pin 4 ? standby supply voltage v stdby in standby mode, only the clock oscillator is active, gnd f should be ground reference. please activate resq before powering-up other supplies pins 6 and 5 ? xtal1 crystal input and xtal2 crystal output (fig. 4 ? 8) these pins are connected to an 20.25 mhz crystal oscillator which is digitally tuned by integrated shunt capacitances. the clk20 and clk5 clock signals are derived from this oscillator. an external clock can be fed into xtal1. in this case, clock frequency adjust- ment must be switched off. pin 7 ? ground, analog front-end gnd f pin 9 ? ground, output pad circuitry gnd p pin 10 ? interlace output, intlc (fig. 4 ? 4) this pin supplies the interlace information, 0 indicates first field, 1 indicates second field. 53 fpdat in/out lv front-end/back-end data 54 resq in x reset input, active low 55 sda in/out x i 2 c bus data 56 scl in/out x i 2 c bus clock 57 test in gnd d test pin, connect to gnd d 58 vin4 in vrt video 4 analog input 59 gnd f supply x ground, analog front-end 60 vin3 in vrt video 3 analog input 61 vin2 in vrt video 2 analog input 62 vin1 in vrt* video 1 analog input 63 cin in lv* chroma/video 4 analog input 64 vout out lv analog video output 65 asgf x analog shield gnd f 66 v supf supply x supply voltage, analog front-end 67 isgnd supply x signal ground for analog input, connect to gnd f 68 vrt output x reference voltage top, analog 8, 11 27, 32 33, 37 44, 45 nc ? lv or gnd d not connected pin no. plcc 68-pin pin name type connection (if not used ) short description
vpc 3205c, vpc 3215c preliminary data sheet 34 micronas pin 12 ? vertical sync pulse, vs (fig. 4 ? 4) this pin supplies the vertical sync signal. pin 13 ? front sync pulse, fsy (fig. 4 ? 4) this pin supplies the front sync information. pin 14 ? main sync/horizontal sync pulse msy/hs (fig. 4 ? 4) this pin supplies the horizontal sync pulse information in line-locked mode. in digit3000 mode, this pin is the main sync input. pin 15 ? helper line output, helper (fig. 4 ? 4) this signal indicates a helper line in pal+ mode. pin 16 ? horizontal clamp pulse, hc (fig. 4 ? 4) this signal can be used to clamp an external video sig- nal, that is synchronous to the input signal. the timing is programmable. pin 17 ? active video output, avo (fig. 4 ? 4) this pin indicates the active video output data. the signal is clocked with the llc1 clock. pin 18 ? double output clock, llc2 (fig. 4 ? 6) pin 19 ? output clock, llc1 (fig. 4 ? 6) this is the clock reference for the luma, chroma, and status outputs. pin 26 ? ground, output pad circuitry gnd p pins 20 to 25,28,29 ? luma outputs y0 ? y7 (fig. 4 ? 4) these output pins carry the digital luminance data. the data are clocked with the llc1 clock. pin 30 ? main clock output clk20 (fig. 4 ? 5) this is the 20.25 mhz main clock output. pin 31 ? supply voltage, digital circuitry v supd pin 34 ? ground, digital circuitry gnd d pin 35 ? ground, output pad circuitry gnd p pin 36 ? supply voltage, output pad supply v supp pins 38 to 43,46,47 ? chroma outputs c0 ? c7 (fig. 4 ? 4) these outputs carry the digital crcb chrominance data. the data are clocked with the ll1 clock. the data are sampled at half the clock rate and multiplexed. the crcb multiplex is reset for each tv line. pins 48 to 50 ? picture bus priority pr0 ? pr2 (fig. 4 ? 6) the picture bus priority lines carry the digital priority selection signals. the priority interface allows digital switching of up to 8 sources to the back-end processor. switching for different sources is prioritized and can be on a per pixel basis. pin 51 ? ground, output pad circuitry gnd p pin 52 ? vgav-input. (fig. 4 ? 3) this pin is connected to the vertical sync signal of a vga signal. pin 53 ? front-end/back-end data fpdat (fig. 4 ? 6) this pin interfaces to the ddp 3300a back-end pro- cessor. the information for the deflection drives and for the white drive control, i.e. the beam current limiter, is transmitted by this pin. pin 54 ? reset input resq (fig. 4 ? 3) a low level on this pin resets the vpc 32xx. pin 55 ? i 2 c bus data sda (fig. 4 ? 13) this pin connects to the i 2 c bus data line. pin 56 ? i 2 c bus clock scl (fig. 4 ? 3) this pin connects to the i 2 c bus clock line. pin 57 ? test input test (fig. 4 ? 3) this pin enables factory test modes. for normal opera- tion, it must be connected to ground. pin 59 ? ground, analog front-end gnd f pins 62,61,60,58 ? video input 1 ? 4 (fig. 4 ? 12) these are the analog video inputs. a cvbs or s-vhs luma signal is converted using the luma (video 1) ad converter. the vin1 input can also be switched to the chroma (video 2) adc. the input signal must be ac-coupled. pin 63 ? chroma input cin (fig. 4 ? 10) this pin is connected to the s-vhs chroma signal. a resistive divider is used to bias the input signal to the middle of the converter input range. cin can only be connected to the chroma (video 2) a/d converter. the signal must be ac-coupled. pin 64 ? analog video output, vout (fig. 4 ? 7) the analog video signal that is selected for the main (luma, cvbs) adc is output at this pin. an emitter fol- lower is required at this pin. pin 65 ? ground, analog shield front-end gnd f pin 66 ? supply voltage, analog front-end v supf (fig. 4 ? 9) pin 67 ? signal gnd for analog input isgnd (fig. 4 ? 11) this is the high quality ground reference for the video input signals. pin 68 ? reference voltage top vrt (fig. 4 ? 9) via this pin, the reference voltage for the a/d converters is decoupled. the pin is connected with 10 f/47 nf to the signal ground pin.
preliminary data sheet vpc 3205c, vpc 3215c micronas 35 4.4. pin configuration fig. 4 ? 2: 68-pin plcc package 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9 8 7 6 5 4 3 2 1 6867666564636261 26 44 vpc 32x5c intlc nc vs fsy msy/hs helper hc avo llc2 llc1 y7 y6 y5 y4 y3 y2 vin3 gndf vin4 test scl sda resq fpdat vgav gndp pr2 pr1 pr0 c0 c1 nc nc gndf xtal1 xtal2 vstby clk5 gndf gndf gndp vrt isgnd vsupf asgf vout cin vin1 vin2 y1 y0 clk20 vsupd nc nc gndd nc vsupp nc c7 c6 c5 c4 c3 c2 gndp gndp nc
vpc 3205c, vpc 3215c preliminary data sheet 36 micronas 4.5. pin circuits fig. 4 ? 3: input pins resq, test, vgav fig. 4 ? 4: output pins c0 ? c7, y0 ? y7, fsy, hc, avo, helper, vs, intlc, hs, llc1, llc2 fig. 4 ? 5: output pin clk20 fig. 4 ? 6: input/output pins pr0 ? pr2, fpdat fig. 4 ? 7: output pin vout fig. 4 ? 8: input/output pins xtal1, xtal2 fig. 4 ? 9: pins vrt, isgnd fig. 4 ? 10: chroma input cin fig. 4 ? 11: output pin clk5 fig. 4 ? 12: input pins vin1 ? vin4 fig. 4 ? 13: pins sda, scl v supd gnd d gnd p p n v supp p n v supd gnd d v supd p n p n v supd n p n gnd d v supf gnd f p n v out v in ? s v ref ? + gnd f v stby p n p n f eclk 0.5m v supf p isgnd vrt vref adc reference ? + gnd f v supf to adc gnd f p n v stby gnd f v supf to adc gnd d
preliminary data sheet vpc 3205c, vpc 3215c micronas 37 4.6. electrical characteristics 4.6.1. absolute maximum ratings stresses beyond those listed in the ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions beyond those indicated in the ? recommended operating conditions/characteristics ? of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 4.6.2. recommended operating conditions symbol parameter pin no. min. max. unit t a ambient operating temperature ? 065 c t s storage temperature ?? 40 125 c v sup supply voltage, all supply inputs ?? 0.3 6 v v i input voltage, all inputs ?? 0.3 v sup +0.3 v v o output voltage, all outputs ?? 0.3 v sup +0.3 v symbol parameter pin name min. typ. max. unit t a ambient operating temperature ? 0 ? 65 c v sup supply voltages, all supply pins ? 4.75 5.0 5.25 v v supp supply volt., output pad supply vsupp 3.15 ? 5.25 v f xtal clock frequency xtal1/2 ? 20.25 ? mhz
vpc 3205c, vpc 3215c preliminary data sheet 38 micronas 4.6.3. recommended crystal characteristics symbol parameter min. typ. max. unit t a operating ambient temperature 0 ? 65 c f p parallel resonance frequency with load capacitance c l = 13 pf ? 20.250000 ? mhz ? f p /f p accuracy of adjustment ?? 20 ppm ? f p /f p frequency temperature drift ?? 30 ppm r r series resistance ?? 25 ? c 0 shunt capacitance 3 ? 7pf c 1 motional capacitance 20 ? 30 ff load capacitance recommendation c lext external load capacitance 1) from pins to ground (pin names: xtal1 xtal2) ? 3.3 ? pf dco characteristics 2,3) c icloadmin effective load capacitance @ min. dco ? position, code 0, package: 68plcc 34.35.5pf c icloadrng effective load capacitance range, dco codes from 0..255 11 12.7 15 pf 1) remarks on defining the external load capacitance: external capacitors at each crystal pin to ground are required. they are necessary to tune the effective load capacitance of th e pcbs to the required load capacitance c l of the crystal. the higher the capacitors, the lower the clock frequency results. the nominal free running frequency should match f p mhz. due to different layouts of customer pcbs the matching capacitor size should be determined in the application. the suggested value is a figure based on experience with various pcb layouts. tuning condition: code dvco register= ? 720 2) remarks on pulling range of dco: the pulling range of the dco is a function of the used crystal and effective load capacitance of the ic (c icload +c loadboard ). the resulting frequency f l with an effective load capacitance of c leff = c icload + c loadboard is: 1 + 0.5 * [ c 1 / (c 0 + c l ) ] f l = f p * _______________________ 1 + 0.5 * [ c 1 / (c 0 + c leff ) ] 3) remarks on dco codes the dco hardware register has 8 bits, the fp control register uses a range of ? 2048...2047
preliminary data sheet vpc 3205c, vpc 3215c micronas 39 4.6.4. characteristics at t a = 0 to 65 c, v supd/f = 4.75 to 5.25 v, v supp = 3.15 to 3.5v f = 20.25 mhz for min./max. values at t c = 60 c, v supd/f = 5 v, vsupp = 3.15v f = 20.25 mhz for typical values 4.6.4.1. characteristics, 5 mhz clock output 4.6.4.2. characteristics, 20 mhz clock input/output, external clock input (xtal1) 4.6.4.3. characteristics, reset input, test input symbol parameter pin name min. typ. max. unit p tot total power dissipation ?? 1.15 1.5 w i vsupa current consumption v supf ? 40 ? ma i vsupd current consumption v supd ? 160 ? ma i vsupp current consumption v supp ? 40 ? ma i vstdby current consumption v stdby ? 1 ? ma il input / output leakage current all i/o pins ? 1 ? 1 a symbol parameter pin name min. typ. max. unit test conditions v ol output low voltage clk5 ?? 0.4 v i ol = 0.4 ma v oh output high voltage 4.0 ? v ? stdby v ? i ol = 0.9 ma t ot output transition time ? 50 ? ns c load = 30 pf symbol parameter pin name min. typ. max. unit test conditions v dcav dc average clk20 v sup /2 ? 0.3 v sup /2 v sup /2 + 0.3 vc load = 30 pf v pp v out peak to peak 1.3 1.6 ? vc load = 30 pf t ot output transition time ?? 18 ns c load = 30 pf v it input trigger level 2.1 2.5 2.9 v only for test purposes v i clock input voltage xtal1 1.3 ?? v pp capacitive coupling used, xtal2 open symbol parameter pin name min. typ. max. unit test conditions v il input low voltage resq test ?? 1.5 v v ih input high voltage 3.0 ?? v
vpc 3205c, vpc 3215c preliminary data sheet 40 micronas 4.6.4.4. characteristics, priority, fpdat input/output fig. 4 ? 14: priority, fpdat input/output 4.6.4.5. characteristics, vgav input symbol parameter pin name min. typ. max. unit test conditions v ol output low voltage pr[2:0] fpdat ?? 0.5 v i ol = 14.4 ma, strength 0 i ol = 10.8 ma, strength 1 i ol = 7.2 ma, strength 2 i ol = 3.6 ma, strength 3 note: fpdat strength = 2 v oh output high voltage 1.8 2.0 2.5 v ? i ol = 10 a c load = 70 pf t oh output hold time 6 ?? ns t odl output delay time ?? 35 ns c load = 70 pf i l = 14.4 ma strength = 3 i pl output pull-up current pr[2:0] fpdat 1.2 1.5 1.5 ma v ol = 0 v v il input low voltage ?? 0.8 v v ih input high voltage 1.5 ?? v t is input setup time 7 ?? ns t ih input hold time 5 ?? ns v ih 20.25 mhz clock v il v ohtri v ol t odl t oh t oh t is t ih priority bus output priority bus input symbol parameter pin name min. typ. max. unit test conditions v il input low voltage vgav ?? 0.8 v v ih input high voltage 2.0 ?? v
preliminary data sheet vpc 3205c, vpc 3215c micronas 41 4.6.4.6. characteristics, i 2 c bus interface 4.6.4.7. characteristics, analog video inputs 4.6.4.8. characteristics, analog front-end and adcs symbol parameter pin name min. typ. max. unit test conditions v il input low voltage sda, scl ?? 1.5 v v ih input high voltage 3.0 ?? v v ol output low voltage ?? 0.4 0.6 v v i l = 3 ma i l = 6 ma v ih input capacitance ?? 5pf t f signal fall time ?? 300 ns c l = 400 pf t r signal rise time ?? 300 ns c l = 400 pf f scl clock frequency scl 0 ? 400 khz t low low period of scl 1.3 ?? s t high high period of scl 0.6 ?? s t su data data set up time to scl high sda 100 ?? ns t hd data data hold time to scl low 0 ? 0.9 s symbol parameter pin name min. typ. max. unit test conditions v vin analog input voltage vin1, vin2 vin3, vin4 cin 0 ? 3.5 v c cp input coupling capacitor video inputs vin1, vin2 vin3, vin4 ? 680 ? nf c cp input coupling capacitor chroma input cin ? 1 ? nf symbol parameter pin name min. typ. max. unit test conditions v vrt reference voltage top vrt 2.5 2.6 2.8 v 10 f/10 nf, 1 g ? probe luma ? path r vin input resistance vin1 vin2 vin3 vin4 1 ?? m ? code clamp ? dac=0 c vin input capacitance ? 5 ? pf v vin full scale input voltage vin1 vin2 vin3 vin4 1.8 2.0 2.2 v pp min. agc gain v vin full scale input voltage 0.5 0.6 0.7 v pp max. agc gain agc agc step width ? 0.166 ? db 6-bit resolution= 64 steps f sig =1mhz, ? 2 dbr of max. agc ? gain dnl agc agc differential non-linearity ?? 0.5 lsb
vpc 3205c, vpc 3215c preliminary data sheet 42 micronas v vincl input clamping level, cvbs vin1 vin2 vin3 vin4 ? 1.0 ? v binary level = 64 lsb min. agc gain q cl clamping dac resolution ? 16 15 steps 5 bit ? i ? dac, bipolar v vin =1.5 v i cl ? lsb input clamping current per step 0.7 1.0 1.3 a dnl icl clamping dac differential non- linearity ?? 0.5 lsb chroma ? path r cin input resistance svhs chroma cin vin1 1.4 2.0 2.6 k ? v cin full scale input voltage, chroma 1.08 1.2 1.32 v pp v cindc input bias level, svhs chroma ? 1.5 ? v binary code for open chroma input ? 128 ?? dynamic characteristics for all video-paths (luma + chroma) bw bandwith vin1 vin2 vin3 vin4 810 ? mhz ? 2 dbr input signal level xtalk crosstalk, any two video inputs ?? 56 ? db 1 mhz, ? 2 dbr signal level thd total harmonic distortion ? 50 ? db 1 mhz, 5 harmonics, ? 2 dbr signal level sinad signal to noise and distortion ratio ? 45 ? db 1 mhz, all outputs, ? 2 dbr signal level inl integral non-linearity ?? 1 lsb code density, dc-ramp dnl differential non-linearity ?? 0.8 lsb dg differential gain ?? 3% ? 12 dbr, 4.4 mhz signal on dc-ramp dp differential phase ?? 1.5 deg analog video output v out output voltage out: vout in: vin1 vin2 vin3 vin4 1.7 2.0 2.3 v pp v in = 1 v pp , agc= 0 db agc vout agc step width, vout ? 1.333 ? db 3 bit resolution=7 steps 3 msb ? s of main agc dnl agc agc differential non-linearity ?? 0.5 lsb v outdc dc-level ? 1 ? v clamped to back porch bw v out bandwidth 8 10 ? mhz input: ? 2 dbr of main adc range, c l 10 pf thd v out total harmonic distortion ??? 40 db input: ? 2 dbr of main adc range, c l 10 pf 1 mhz, 5 harmonics c lvo ut load capacitance vout ?? 10 pf i lvout output current ?? 0.1 ma symbol parameter pin name min. typ. max. unit test conditions
preliminary data sheet vpc 3205c, vpc 3215c micronas 43 4.6.4.9. characteristics, output pin specification output specification for sync, control, and data pins: y[7:0], c[7:0], avo, hs, hc, helper, intlc, vs, fsy note 1: c load depends on the selected driver strength which is i 2 c-programmable. fig. 4 ? 15: sync, control, and data outputs symbol parameter pin name min. typ. max. unit test conditions v ol output low voltage ??? 0.4 v see table below v oh output high voltage ? 2.4 ?? v see table below t oh output hold time ? 6 ?? ns t od output delay time ??? 35 ns note 1 table 4 ? 1: driver strength strength v supp = 5 v load v supp = 3.3 v load 000 < 100 pf < 50 pf 001 < 55 pf < 28 pf 010 < 37 pf < 20 pf 011 < 28 pf < 14 pf 100 < 23 pf < 12 pf 101 < 18 pf < 10 pf 110 < 14 pf < 8 pf 111 pins tristate clk20 20.25 mhz in case of digit3000 mode llc1 13.5 mhz in case of llc mode output 2.0 v t r, t f 5 ns 0.8 v v oh v ol data valid t od t oh data valid
vpc 3205c, vpc 3215c preliminary data sheet 44 micronas 4.6.4.10. characteristics, input pin specification input specification for sync, control, and data pin: msy (digit3000 mode only) fig. 4 ? 16: sync, control, and data inputs symbol parameter pin name min. typ. max. unit test conditions v il input low voltage ??? 0.8 v v ih input high voltage ? 1.5 ?? v t is input setup time ? 7 ?? ns t ih input hold time ? 5 ?? ns clk20 20.25 mhz in case of digit3000 mode llc1 13.5 mhz in case of llc mode input input data valid t ih t is data valid t ih t is v ih v il 2.0 v t r, t f 5ns 0.8 v v ih v il
preliminary data sheet vpc 3205c, vpc 3215c micronas 45 4.6.4.11. characteristics, clock output specification line-locked clock pins: llc1, llc2 fig. 4 ? 17: line-locked clock output pins symbol parameter pin name min. typ. max. unit test conditions cl load capacitance ??? 50 pf 13.5 mhz line locked clock 1/t 13 llc1 clock frequency ? 12.5 ? 14.5 mhz t wl13 llc1 clock low time ? 26 ?? ns c l = 30 pf t wh13 llc1 clock high time ? 26 ?? ns c l = 30 pf 1/t 27 llc2 clock frequency ? 25 ? 29 mhz t wl27 llc2 clock low time ? 10 ?? ns c l = 30 pf t wh27 llc2 clock high time ? 10 ?? ns c l = 30 pf 16 mhz line locked clock 1/t 13 llc1 clock frequency ? 14.8 ? 17.2 mhz 18 mhz line locked clock 1/t 13 llc1 clock frequency ? 16.6 ? 19.4 mhz common timings ? all modes t sk clock skew ? 0 ? 4ns t r , t f clock rise/fall time ??? 5nsc l = 30 pf v il input low voltage ??? 0.8 v v ih input high voltage ? 2.0 ?? v v ol output low voltage ??? 0.4 v i l = 2 ma v oh output high voltage ? 2.4 ?? vi h = ? 2 ma (13.5 mhz 7%) (27 mhz 7%) llc2 llc1 v il v ih v il v ih t sk t wl13 t wh13 t 13 t r t f t 27 t wl27 t wh27 t sk t r t f
vpc 3205c, vpc 3215c preliminary data sheet 46 micronas 5. application circuit vpc 32x5c
preliminary data sheet vpc 3205c, vpc 3215c micronas 47 5.1. vga mode with vpc3215c in 100 hz tv applications it can be desirable to display a vga-signal on the tv. in this case a vga-graphic card delivers the h, v and rgb signals. these signals can be feed "directly" to the backend signal process- ing. the vpc can generate a stable line locked clock for the 100 hz system in relation to the vga sync sig- nals. while the v-sync is connected to the vgav pin directly, the h-sync has to be pulse-shaped and ampli- tude adjusted until it is connected to one of the video input pins of the vpc. the recommended circuitry to filter the h sync is given in the figure below. fig. 5 ? 1: application circuit for horizontal vga-input 680 nf video input vpc h 31khz 270 ? 47pf 540 ? 1n4148 bc848b 100 ? 1k ? +5v analog 1n4148 2k ? gnd analog gnd analog
vpc 3205c, vpc 3215c preliminary data sheet 48 micronas all information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. any new issue of this data sheet invalidates previous issues. product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples deliv- ered. by this publication, micronas gmbh does not assume responsibil- ity for patent infringements or other rights of third parties which may result from its use. further, micronas gmbh reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. no part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of micronas gmbh. micronas gmbh hans-bunte-strasse 19 d-79108 freiburg (germany) p.o. box 840 d-79008 freiburg (germany) tel. +49-761-517-0 fax +49-761-517-2174 e-mail: docservice@micronas.com internet: www.micronas.com printed in germany order no. 6251-457-2pd 6. data sheet history 1. preliminary data sheet: ? vpc 3205c, vpc 3215c video processor family, aug. 15, 1997 6251-457-1pd. first release of the preliminary data sheet. 2. preliminary data sheet: ? vpc 3205c, vpc 3215c video processor family, oct. 19, 1998, 6251-457-2pd. second release of the preliminary data sheet. major changes: ? fig. 4 ? 1: outline dimensions for plcc68 changed. ? additional information contained in supplement no.3 / 6251-457-3pds, edition may 25 1998 has been included.

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